Decoder circuit using magnetic core elements and driving a decimal display device



3,449,740 AND June 10, 1969 J. A. LOCKHART, JR

' DECODER CIRCUIT USING MAGNETIC CORE ELEMENTS DRIVING A DECIMAL DISPLAY DEVICE Sheet of2 Filed Feb.

INVENTOR. JAMES A. LOCKHARIJr.

ATTORNEY June 10, 1369 DECODER CIRCUIT USING MAGNETTC CORR ELEMENTS AND DRIVING A DECIMAL DISPLAY DEVICE Sheet 2 012 Filed Feb. 5, 1965 J A. LOCKHART, JR 3,449,740

. INVENTOR. JAMES A. LOCKHARIJr.

ATTORNEY United States Patent 3,449,740 DECODER CIRCUIT USING MAGNETIC 'CORE ELEMENTS AND DRIVING A DECIMAL DISPLAY DEVICE James A. Lockhart, Jr., Basking Ridge, N.J., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Filed Feb. 3, 1965, Ser. No. 430,074 Int. Cl. H04] 3/02; G061? 5/02; G08c 9/04 US. Cl. 340-347 7 Claims ABSTRACT OF THE DISCLOSURE The disclosure is of a binary-coded decimal to decimal decoder circuit including ten magnetic cores and an oscillator having two output leads, one lead being connected through ten windings, each wound in one polarity on a core, and the second lead being coupled through ten windings, each being wound in the opposite polarity on a core. Four pairs of parallel current flow paths are provided, with each pair including a total of ten inhibit windings, one on each core. The windings are disposed differently on each of the four pairs of paths so that, when binary-coded decimal signals are applied to the four pairs of paths through switches which select one path of each pair, each combination of signals inhibits all but one core and this uninhibited core becomes part of the oscillator and is switched by the oscillator. Each core also carries a winding coupled to a display device for operation thereby.

This invention relates to electronic decoder circuits and, particularly, to decoder circuits which include a display device for displaying the output of the decoding operation and using square loop magnetic core elements for performing the decoding operation.

There are many types of electronic decoder circuits in the prior art, and, in general, they all include 'an indicator or display device for displaying the output of the decoder operation. Usually, the operation converts binary code signals to decimal signals, and the most common type of device for displaying the decimal output is a gaseous cold cathode glow tube such as the type 6844A tube. Generally, this type of tube requires a relatively high voltage power supply of the order of 200 volts for its operation. In addition, some circuits which use transistors to drive the decimal display device require relatively expensive transistors which are able to handle such high voltages. While these are not insurmonutable problems, it is always desirable, particularly from an economic standpoint, to be able to operate electronic circuits with low voltage power supplies, if possible.

Accordingly, the objects of the present invention concern the provision of an improved electronic signal decoder circuit using a relatively high voltage output display device, the circuit being arranged so that it performs the decoder operation and operates the display device without requiring high voltage power supplies.

Briefly, a circuit embodying the invention utilizes bi-' stable magnetic core elements carrying a plurality of windings correlated to provide the desired decoding operation. An oscillator is coupled to all of the cores for alternately setting and resetting the cores. In addition, each core carries an output winding having a large number of turns for generating a voltage large enough to operate an indicator device which requires relatively high voltages for its operation.

The input signal bits, which are assumed to be in binarycoded decimal code and are to be converted to decimal code, are coupled through a switching device and two ice current flow paths to each of the magnetic cores, with the two paths and the windings being arranged so that the conversion of each group of input signals tothe proper decimal output signal is achieved. This operation is manitested by the switching of a single core and the resultant energization of the proper decimal character in the display device.-

The invention is described in greater detail by reference to the drawing, wherein:

FIG. 1 is a schematic representation of a decoder circuit and display device embodying the invention; and

FIG. 2 is a schematic representation of a modification of a portion of the circuit of FIG. 1.

The principles of the invention are shown embodied in a decoder circuit 10 for converting binary-coded decimal signals to pure decimal signals. The circuit includes ten magnetic cores, C0 through C9, which are made of a material having a rectangular hysteresis characteristic which permits the cores to be shifted between two stable states, each of which can be maintained indefinitely. Such cores and materials are well known. Each core carries a plurality of inhibit windings provided thereon in a pattern arranged, according to the principles olf the invention, to perform the required signal conversion operation when groups of binary-coded decimal signal bits are applied to the circuit.

In the circuit 10, it is assumed that the binary-coded decimal signals, which are applied to the circuit, are each made up of four signal bits which are represented by twoposition switches 11, 12, 13, and 14. Each switch is adapted to represent the presence of either a signal bit or its complement, depending on the contact position of the switch. The switches may be mechanical switches as shown in FIG. 1, or they may be electronic switches 62 such as transistors or the like shown in block diagram in FIG. 2. The mechanical switches shown in FIG. 1 include common terminals *18, 19, 20, 21 and movable switch members 24, 25, 26, 27, respectively, with each switch member being adapted to separately contact two terminals 30 and 31, 40 and 41, 50 and 51, and 60 and 61, respectively. The terminals 30 and 31 lead to separate current flow paths 30 and 31, respectively. Similarly, terminals 40 and 41 lead to paths 40 and 41', terminals 50 and 51 lead to paths 50 and 51', and terminals 60 and 61 lead to paths 60' and 61.

In the circuit shown, connection of the contact member of each switch to the left hand path, that is path 30', 40', 50', 60', represents the presence of a signal bit, and connection to the right hand path, that is path 31', 41', 5'1, 61, represents the presence of the complement of the signal bit. In addition, in the order shown, the switches I11, 12, 13, 14 represent correspondingly the 2 2 2 and 2 binary signal bits.

In FIG. 2, each terminal 18, 19, 20 and 21 is coupled through a separate electronic switch 62, such as a triode transistor or tetrode transistor, to each current flow path. Each pair of switches may comprise, for example, a flipflop which can be set to determine which path is blocked and which is open and can pass current.

Referring again to FIG. 1, the specific inhibit winding arrays used to convert binary-coded decimal to decimal signals are as follows. In the first pair of paths coupled to terminal 18, the path 30 includes windings W30 on cores C0, C1, C2, C3, C4, C5, C6, C7, and the path 31 includes windings W31 on cores C8 and C9. In the second pair of paths coupled to terminal 19, the path 40 includes windings W40 on cores C0, C1, C2, C3, C8 and C9, and the path 31' includes windings W31 on cores C4, C5, C6, and C7.

In the third pair of paths coupled to terminal 20, the path 50' includes windings W50 on cores C0, C1, C4, C5, C8, and C9, and the path 51' includes windings W51 on cores C2, C3, C6, and C7. In the fourth pair of paths from 18 are connected by lead 64 to terminal 19. Similarly,

paths 40 and 41' from terminal 19 are connected by lead 68 to terminal 20, and paths 50 and 51 from terminal are connected by lead 72 to terminal 21. Paths 60' and 61" from terminal 21 are connected by lead 76 to I ground to complete the current path.

Each core is also coupled to an oscillator 80 which may be of any suitable type. The oscillator shown includes two triode transistors 84 and 86 which have their emitter electrodes 88, 88 connected together and to the negative terminal of a DC. power supply V0 (about 12 volts), and their bases 90, 90 and collectors 92, 92' cross-connected through resistive paths. In addition, the collector electrode 92 of transistor 84 is coupled through series connected windings 94, one on each core, to the positive terminal of power supply V0. The collector electrode 92' of transistor 86 is similarly coupled through series connected windings 94', one on each core, to the positive terminal of power supply V0. With these connections, the oscillator 80 is adapted to alternately set and reset all cores C0 to C9 in each cycle of its operation.

The decoded decimal output of circuit 10 is adapted to be displayed visually by a gaseous glow cathode indicator tube 106 which may be a type 6844A tube. This type of tube, which is shown schematically in the drawing, includes ten indicator cathode electrodes 120, the numbers 0 to 9, and an anode electrode 122. In order to couple the display tube 106 to the aforementioned circuitry, each core is provided with an output winding 130 which has one end connected through a diode 134 oriented as shown, to one glow cathode 120, and the other end is connected to a bus 138 which is connected in turn through a resistive path to the anode 122. Each output winding has a sufiicient number of turns so that, when its core is switched by the oscillator 80, a voltage is generated therein which is of suflicient magnitude to cause the associated cathode to glow when it is applied between the cathode and the anode.

' Operation of the circuit of the invention is as follows. When a group of signal bits having a binary-coded decimal representation is applied to the circuit, the switches 11, 12, 13, 14 are set accordingly to represent the presence of a signal bit or its complement. With the switches set in accordance with the combination of signal bits, inhibit current flows through windings on all but one core, which windings appear as short circuits and all cores are prevented from switching except this one core. This one core operates with transistors 90 and 90 to cause oscillator 80 to operate, and the oscillator switches the one uninhibited core and generates a voltage in its output winding 130 which is sufficiently large to cause the associated glow cathode in tube 106 to glow.

Consider a specific decoding operation. Assume that the signal bits are 0000 which together represent decimal zero. With these signal bits applied, all switches contact the complement flow paths, through the terminals 31, 41, 51, and 61, respectively, and it can be seen that only the core C0 has no inhibit current flow through any of its windings. Thus, each time the oscillator sets core C0, a voltage is generated in its output winding which is applied between anode 122 and cathode numeral zero,

I and the cathode glows.

Similarly, hits 0001 having a representation of decimal one set the switches in contact with terminals 30, 41,

51 and 61 so that inhibit current flows in all cores except core C1 which causes cathode numeral one to glow. (In the same way, various other combinations of input signal bits will provide a single corresponding visual display of the decoding operation. In each case, the uninhibited core becomes an operating component of oscillator 80.

What is claimed is:

1. A binary-coded decimal to decimal decoder circuit comprising ten magnetic cores,

four pairs of parallel current flow paths, each pair of paths including a total of ten inhibit windings for inhibiting core operation, one inhibit winding being wound on each core, the distribution ofthe windings in each pair or paths being diiferent,

means coupled to said paths for connecting them in diflerent combinations such that for each combination, all cores but one are inhibited by current flo through said inhibit windings,

a set and reset winding pair on each core,

electronic switching means connected to said set and reset winding pairs on all of said cores, each combination of said switching means with one of said winding pairs and a core comprising an oscillator whereby, for each signal decoding operation, said electronic switching means joins with the winding pair on said one uninhibited core to provide an oscillator which operates to set and reset said one uninhibited core, and

an output winding on each of said magnetic cores for providing an output signal from the one uninhibited core which permits said oscillator to operate in each signal decoding operation. 2. The circuit defined in claim 1 wherein the cores occupy positions numbered 0, 1, 2, 3 9, and

wherein the first pair of paths is associated with the 2 signal bit and one path includes a switch and inhibit windings on cores at positions 0, 2, 4, 6, and 8, and the other path includes inhibit windings on cores at positions 1, 3, 5, 7, and 9,

the second pair of paths is associated with the 2 signal bit and one path includes a switch and inhibit windings on cores at positions 0, 1, 4, 5, 8 and 9, and the other path includes inhibit windings on cores at positions 2, 3, 6, and 7,

the third pair of paths is associated with the 2 signal bit and one path includes a switch and inhibit windings on cores at positions 0, 1, 2, 3, 8, and 9, and the other path includes inhibit windings on cores at positions 4, 5, 6, and 7, and

the fourth pair of paths is associated with the 2 signal bit and one path includes a switch and inhibit windings on cores at positions 0, 1, 2, 3, 4, 5, 6, and 7, and the other path includes inhibit windings on cores at positions 8 and 9.

3. The circuit defined in claim 1 and including a display device coupled to each said output winding for providing a visual display representing switching of said one uninhibited core by said oscillator.

4. The circuit defined in claim 1 wherein said switching windings are arranged in two paths, each including ten windings with the windings in one path connected in one polarity and the windings in the other connected in the opposite polarity.

5. The circuit defined in claim 1 and including a switch associated with each said pair of current'flow paths and adapted to be connected to one path or the other in each pair,

a connection from the first pair of paths to the switch of the second pair and from the second pair to the switch of the third pair and from the third pair to the switch of the fourth pair so that one path of each pair can be connected in a series circuit,

each combination of paths which can be connected in series having an inhibit winding on every core except one, said one core being an operating component of said oscillator.

6. A signal decoder circuit comprising a plurality of magnetic cores,

a plurality of inhibit windings wound on said cores and arrayed in current flow paths to which signal bits can be connected in diflerent combinations such that, when a group of signal bits is coupled to said paths, all but one of said cores is inhibited from switching,

a set and reset winding pair on each core,

electronic switching means connected to said set and reset winding pairs on all of said cores, each combination of said switching means with one of said winding pairs and a core comprising an oscillator whereby, for each signal decoding operation, said electronic switching means joins with the winding pair on said one uninhibited core to provide an oscillator which operates to set and reset said one uninhibited core, and

References Cited UNITED STATES PATENTS 2/1957 Rajchman 340347 X 6/1963 Lynch 340347 MAYNARD R. WILBUR, Primary Examiner.

GARY R. EDWARDS, Assistant Examiner.

US. Cl. X.R. 235-155 

